Template:Asic/sandbox

ASICMiner

ASICMiner Facilitators: BitQuan,BitFountain	Top Bottom
BE100 BCT Introduced: 2012-Dec-28
Technical specifications Package: Sawn QFN40 6x6mm Markings: BE100 Die:4.66x4.66mm@130nm	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 0.336 6 167 1.05 336 2.016 1 0.02 4249.2 0.392 8 125 1.15 392 3.136 1 0.02 4957.4
Notes: The letters 'BE' in the component name/markings stands for "Block Erupter". ASICMiner considers the BE100 their 'Gen1' product.
Used on: Block Erupter USB, Block Erupter Cube, Block Erupter Blade

ASICMiner unknown BCT Facilitators: BitQuan,BitFountain Planned: 2012-Nov	No pictures available Die:65nm
Canceled (see notes for details)
Notes: This chip would formally have been ASICMiner's 'Gen2' product. Development appears to have been canceled prior to production.

ASICMiner Facilitators: BitQuan,BitFountain	Top (8x8mm) Bottom (9x9mm)
BE200www BCT Introduced: 2014-Mar-28 Datasheet: package dimensions,pins/protocol, pinout
Technical specifications Package: Sawn QFN64 8x8mm Markings: BE200 / [lot] Known codes: lot:8P01N,9C01H,9P02A,9P02H Die:40nm	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 9.6 0.66 1515 0.8 6.336
Notes: ASICMiner considers this their 'Gen3' product. Was made available in 8x8mm and 9x9mm packages.
Used on: ASICMiner Tube, ASICMiner Prisma

ASICMiner Facilitators: BitQuan,BitFountain	Top Layout
BE300S prototype BCT Introduced: 2014-Sep-16
Technical specifications Package: Sawn QFN40* Markings: BE300S Die:28nm Foundry: TSMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 3 0.187 5342 0.5616 5.2 0.247 4050 1.28388
Notes: This was a prototype manufactured on an MPW. The package appears to be soldered on only 2 sides, which may imply that internally there are also only bond wires to those two sides.

ASICMiner BE300(S) BCT Facilitators: BitQuan,BitFountain Planned: 2015-Feb	No pictures available Package: FCLGA 5x5mm Die:28nm Foundry: TSMC
May not actually exist (see notes for details)	Mining: 8Gh/s 0.038J/Gh, 12Gh/s 0.038J/Gh, 6Gh/s 0.033J/Gh, 9Gh/s 0.022J/Gh
Notes: ASICMiner would consider this their 'Gen4' product. The expected hashing performance and package size is preliminary. The BE300(S) is understood not to be in production at this time.

ASICMiner Unknown Facilitators: BitQuan,BitFountain Planned: 2015	No pictures available Die:16nm
Future (see notes for details)
Notes: The planned node size would be 16nm or 14nm This chip is planned to be introduced in the future.

Avalon Project

Avalon Project Facilitators: Canaan Creative, BitSynCom	top bottom Layout Die (power) Die (cores)
A3256www BCT Introduced: 2013-Jan-20 Datasheet: datasheet, package
Technical specifications Package: Sawn QFN48 7x7mm Markings: Old Avalon logo / A3256-Q48 / [lot/date] Known codes: P6M56213042C,P6M56313052C,PP787813212 Die:3.976x4.056mm@110nm Foundry: TSMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 0.295 6.6 152 1.15 375 1.947 0.79 0.02 3043.45
Notes: First ASIC to be put to market, with first delivery of a miner to Jeff Garzik.

Avalon Project Facilitators: Canaan Creative, BitSynCom	Top
A3255www BCT Introduced: 2013-Aug Datasheet: datasheet, package
Technical specifications Package: Sawn QFN48 7x7mm Markings: Avalon logo / A3255-Q48 / [lot/date] Known codes: SKWL0613452CMU Die:55nm Foundry: TSMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 1.5 1.6 625 0.8 750 2.4 2 1.5 2.45 408 1.0 750 3.675 2

Avalon Project Facilitators: Canaan Creative, BitSynCom	Top Bottom
A3233www Introduced: 2014-Apr Datasheet: datasheet, package
Technical specifications Package: Sawn QFN48 7x7mm Markings: Avalon logo / A3233-Q48 / [lot/date] Known codes: P6P73914092CMU,P6P73914102CAL Die:40nm Foundry: TSMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 7.08 0.75 1333 0.55 600 5.31 11.8 7.08 0.89 1124 0.89 600 6.3012 11.8

Avalon Project Facilitators: Canaan Creative, Alchip Technologies, Ltd	Top
A3222www BCT Introduced: 2014-Sep Datasheet: datasheet, package
Technical specifications Package: Sawn QFN56 8x8mm Markings: Avalon logo / A3222-Q56 / [lot/date] Known codes: T8A98911434EMAA,T4V9181435ECLA Die:28nm Foundry: TSMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 25 0.4 2500 0.65 400 10 62.5 25 0.6 1667 0.8 400 15 62.5

BitFury Group

BitFury Group Facilitators: IMEC,Europractice,BioInfoBank Institute	Tops/Bottom Layout Layout Die (optical) Die (power) Die (cores)
BF756C55www BCT Introduced: 2013-Jun-14 Datasheet: datasheet package pinout compilation
Technical specifications Package: Sawn/Punched QFN48 7x7mm Markings: β: β / 5Ghash / [date] / [lot] / TT BioInfoBank: BioInfoBank logo / BIB756C55NM-BF / [date] / [lot] CCCP: CCCP logo / CCCP756C55NM-BF / [date] / [lot] Known codes: β: KRT8G, BioInfoBank: 1336/KYG0H, 1404/KCKCL, CCCP: 1340/KYW3Q Die:3.8x3.8mm@55nm(full custom+global place&route) Foundry: UMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 5.43 0.38 2632 0.687 467 2.0634 11.63 0.38 7820.43 4.77 0.35 2857 0.65 410 1.6695 11.63 0.33 6869.88 3.26 0.25 4000 0.545 280 0.815 11.64 0.23 4695.14 2.5 0.21 4762 0.5 216 0.525 11.57 0.17 3600.57
Notes: BitFury Group considers this their Gen 1, Rev 1 product. It was originally designed at 65nm but die-shrunk down to 55nm. It was widely released in at least 3 different packages/markings: The 'beta' / 5Ghash (estimated hash rate before practical tests) markings on a sawn package, BioInfoBank and CCCP markings on a punched package. BitcoinTalk user vs3 holds a large collection of technical information about this chip in his NanoFury repository

BitFury Group Facilitators: IMEC,Europractice	Top Bottom
BF864C55www BCT Introduced: 2014-Mar-03
Technical specifications Package: Punched QFN48 7x7mm Markings: BitFury Logo / BF864C55 / [lot] Known codes: KCYLT,KCTMS Die:55nm(full custom) Foundry: UMC	Gh/s J/Gh Mh/J V MHz W h/Hz Gh/mm² η-factor 3.8 0.5 2000 0.5 1.2
Notes: BitFury Group considers this their Gen 1, Rev 2 product. This chip is pin- and protocol-compatible with the BF756C55, allowing many existing designs based on the BF756C55 to be upgraded.