Open Source FPGA Bitcoin Miner: Difference between revisions
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A miner that makes use of a compatible FPGA Board. The miner works either in a [[Pooled Mining|mining pool]] or solo. | A miner that makes use of a compatible FPGA Board. The miner works either in a [[Pooled Mining|mining pool]] or solo. | ||
This is the first open source FPGA | This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011<ref>[http://bitcointalk.org/index.php?topic=9047.0 Official Open Source FPGA Bitcoin Miner (Just Released!)]</ref>. | ||
== Software needed == | |||
Currently programming and running the FPGAminer code requires Quartus II for Altera devices and Xilinx ISE Webpack for Xilinx devices. Quartus is 32bit only. The free ISE Webpack does not work on devices larger then Spartan6 LX75. | |||
== Compiling == | == Compiling == | ||
=== Altera === | === Altera === | ||
The compile the code on an different Altera device then DE2-115, you need to set the Device to be the correct one. Find the correct fpga package number and add it, for the DE0-Nano this is EP4CE22F17C6. Be sure to select the correct one, because the hardware effects the location of your pins, which you will need in the clock pin step. | |||
To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf. | To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf. | ||
To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. ''This can be read from the device manual''! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you ''must'' look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin ''specified in your manual'', ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2. | |||
=== Changing the clock speed === | |||
NOTE: You can fry your FPGA doing this! | |||
Edit main_pll.v and find the line: | |||
altpll_component.clk0_multiply_by = 5, | |||
The way the Mhz is calculated is 50Mhz*multply_by/divide_by. Setting of 10 with default clk0_divide_by gives Mhz of 100, 8 is 80Mhz. | |||
Compile the code. | |||
Watch for critical warnings from synthesis. | |||
Run Powerplay power analyzer tool and set it with the cooling system you have. If there are no errors, you may at your own risk program the FPGA with the higher Mhz bitfile. | |||
== Programming the FPGA == | == Programming the FPGA == | ||
On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules. | |||
#####altera usb blaster | |||
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster" | |||
=== Altera === | === Altera === | ||
Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory. | Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory. | ||
== | === Using urjtag === | ||
(unconfirmed to work, lights blink though) | |||
$ sudo jtag | |||
> cable UsbBlaster | |||
> bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd | |||
> detect | |||
> svf fpgaminer.svf | |||
== Mining == | |||
=== Altera === | |||
The new mining and programming scripts find the connected devices now. Just edit the config.tcl to have your details. | |||
==See Also== | ==See Also== | ||
| Line 43: | Line 71: | ||
* [http://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner Open-Source-FPGA-Bitcoin-Miner] project on GitHub | * [http://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner Open-Source-FPGA-Bitcoin-Miner] project on GitHub | ||
* [http://www.bitcoinmining.com/bitcoin-mining-software/ Bitcoin Mining Software] | |||
==References== | ==References== | ||
Latest revision as of 02:09, 10 June 2019
A miner that makes use of a compatible FPGA Board. The miner works either in a mining pool or solo.
This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011[1].
Software needed
Currently programming and running the FPGAminer code requires Quartus II for Altera devices and Xilinx ISE Webpack for Xilinx devices. Quartus is 32bit only. The free ISE Webpack does not work on devices larger then Spartan6 LX75.
Compiling
Altera
The compile the code on an different Altera device then DE2-115, you need to set the Device to be the correct one. Find the correct fpga package number and add it, for the DE0-Nano this is EP4CE22F17C6. Be sure to select the correct one, because the hardware effects the location of your pins, which you will need in the clock pin step.
To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf.
To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. This can be read from the device manual! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you must look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin specified in your manual, ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2.
Changing the clock speed
NOTE: You can fry your FPGA doing this!
Edit main_pll.v and find the line: altpll_component.clk0_multiply_by = 5,
The way the Mhz is calculated is 50Mhz*multply_by/divide_by. Setting of 10 with default clk0_divide_by gives Mhz of 100, 8 is 80Mhz.
Compile the code.
Watch for critical warnings from synthesis.
Run Powerplay power analyzer tool and set it with the cooling system you have. If there are no errors, you may at your own risk program the FPGA with the higher Mhz bitfile.
Programming the FPGA
On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules.
#####altera usb blaster
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster"
Altera
Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory.
Using urjtag
(unconfirmed to work, lights blink though)
$ sudo jtag
> cable UsbBlaster
> bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd
> detect
> svf fpgaminer.svf
Mining
Altera
The new mining and programming scripts find the connected devices now. Just edit the config.tcl to have your details.
See Also
External Links
- Open-Source-FPGA-Bitcoin-Miner project on GitHub
- Bitcoin Mining Software