Difference between revisions of "Avalon2"

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(FPGA controller)
(FPGA controller)
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== FPGA controller ==
 
== FPGA controller ==
About TIMEOUT value please read [http://downloads.canaan-creative.com/hardware/A3255/prototype/FPGA/2013-11-05/README here]
+
=== TIMEOUT ===
=== [http://downloads.canaan-creative.com/hardware/A3255/prototype/FPGA/2013-11-05/ 2013-11-05] ===
+
* TIMEOUT的有效值范围为[0,255],FPGA controller根据TIMEOUT的配置来控制申请/计算任务的时间。当TIMEOUT值配置为1时,FPGA controller会每隔0.033s申请一次任务,也表示芯片已计算完当前HASH区间。
 +
* TIMEOUT配置与申请/计算任务时间间隔的公式为
 +
  TIME_OF_MINER_FINISH_HASH_RANGE = TIMEOUT * 0.033s
 +
  TIMEOUT = TIME_OF_MINER_FINISH_HASH_RANGE / 0.033s
 +
 
 +
* 若FPGA controller连接的一个小模块上的计算能力为10GHs(10个芯片,每芯片1G),则FPGA controller申请任务的时间间隔为
 +
  2^32 / 10*1000*1000*1000 = 0.4s
 +
  0.4s/0.033s = 12 # TIMEOUT应配置为12
 +
 
 +
=== [http://downloads.canaan-creative.com/hardware/A3255/prototype/FIRMWARE/2013-11-05/ 2013-11-05] ===
 
* Update for A3255 controller
 
* Update for A3255 controller
 
* Support 8, 16, 24, 32 miners, '''8 and 16 have tested'''
 
* Support 8, 16, 24, 32 miners, '''8 and 16 have tested'''
 
* Support 6 ~ 10  chip in each miner, '''6 and 10 have tested'''.
 
* Support 6 ~ 10  chip in each miner, '''6 and 10 have tested'''.
  
=== [http://downloads.canaan-creative.com/hardware/A3255/prototype/FPGA/2013-10-07/ 2013-10-07] ===
+
=== [http://downloads.canaan-creative.com/hardware/A3255/prototype/FIRMWARE/2013-10-07/ 2013-10-07] ===
 
* Only support 16 miners, each miner have 6 A3255
 
* Only support 16 miners, each miner have 6 A3255
 
* Cgminer: https://github.com/BitSyncom/cgminer/tree/avalon-55nm, https://github.com/BitSyncom/cgminer/commit/9d9450628923337646f4c50c1efd42652c97c7f9
 
* Cgminer: https://github.com/BitSyncom/cgminer/tree/avalon-55nm, https://github.com/BitSyncom/cgminer/commit/9d9450628923337646f4c50c1efd42652c97c7f9

Revision as of 10:09, 10 November 2013

Avalon2 is the second machine of Avalon project. using the 55nm ASIC chips

Prototype

Avalon2 55nm prototype.jpeg

FPGA controller

TIMEOUT

  • TIMEOUT的有效值范围为[0,255],FPGA controller根据TIMEOUT的配置来控制申请/计算任务的时间。当TIMEOUT值配置为1时,FPGA controller会每隔0.033s申请一次任务,也表示芯片已计算完当前HASH区间。
  • TIMEOUT配置与申请/计算任务时间间隔的公式为
 TIME_OF_MINER_FINISH_HASH_RANGE = TIMEOUT * 0.033s
 TIMEOUT = TIME_OF_MINER_FINISH_HASH_RANGE / 0.033s
  • 若FPGA controller连接的一个小模块上的计算能力为10GHs(10个芯片,每芯片1G),则FPGA controller申请任务的时间间隔为
 2^32 / 10*1000*1000*1000 = 0.4s
 0.4s/0.033s = 12 # TIMEOUT应配置为12

2013-11-05

  • Update for A3255 controller
  • Support 8, 16, 24, 32 miners, 8 and 16 have tested
  • Support 6 ~ 10 chip in each miner, 6 and 10 have tested.

2013-10-07

Links