Open Source FPGA Bitcoin Miner - Revision history

Gmaxwell: fix links

2019-06-10T02:09:23Z

fix links

← Older revision		Revision as of 02:09, 10 June 2019
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	A miner that makes use of a compatible FPGA Board. The miner works either in a [[Pooled Mining\|mining pool]] or solo.		A miner that makes use of a compatible FPGA Board. The miner works either in a [[Pooled Mining\|mining pool]] or solo.

	This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011<ref>[http://~~forum.bitcoin~~.org/index.php?topic=9047.0 Official Open Source FPGA Bitcoin Miner (Just Released!)]</ref>.		This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011<ref>[http://bitcointalk.org/index.php?topic=9047.0 Official Open Source FPGA Bitcoin Miner (Just Released!)]</ref>.

	== Software needed ==		== Software needed ==

Sunnankar: /* External Links */ References

2015-06-01T01:31:05Z

External Links: References

← Older revision		Revision as of 01:31, 1 June 2015
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	* [http://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner Open-Source-FPGA-Bitcoin-Miner] project on GitHub		* [http://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner Open-Source-FPGA-Bitcoin-Miner] project on GitHub
			* [http://www.bitcoinmining.com/bitcoin-mining-software/ Bitcoin Mining Software]

	==References==		==References==

Luke-jr: Luke-jr moved page Open Source FGPA Bitcoin Miner to Open Source FPGA Bitcoin Miner: Typo

2014-08-18T11:06:46Z

Luke-jr moved page Open Source FGPA Bitcoin Miner to Open Source FPGA Bitcoin Miner: Typo

← Older revision	Revision as of 11:06, 18 August 2014
(No difference)

Fikaloii: added clock speed modifications

2011-08-11T18:37:57Z

added clock speed modifications

← Older revision		Revision as of 18:37, 11 August 2011
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	To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. ''This can be read from the device manual''! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you ''must'' look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin ''specified in your manual'', ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2.		To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. ''This can be read from the device manual''! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you ''must'' look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin ''specified in your manual'', ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2.

			=== Changing the clock speed ===

			NOTE: You can fry your FPGA doing this!

			Edit main_pll.v and find the line:
			altpll_component.clk0_multiply_by = 5,

			The way the Mhz is calculated is 50Mhz*multply_by/divide_by. Setting of 10 with default clk0_divide_by gives Mhz of 100, 8 is 80Mhz.

			Compile the code.

			Watch for critical warnings from synthesis.

			Run Powerplay power analyzer tool and set it with the cooling system you have. If there are no errors, you may at your own risk program the FPGA with the higher Mhz bitfile.

	== Programming the FPGA ==		== Programming the FPGA ==

Fikaloii at 20:44, 10 August 2011

2011-08-10T20:44:23Z

← Older revision		Revision as of 20:44, 10 August 2011
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	=== Altera ===		=== Altera ===

			The compile the code on an different Altera device then DE2-115, you need to set the Device to be the correct one. Find the correct fpga package number and add it, for the DE0-Nano this is EP4CE22F17C6. Be sure to select the correct one, because the hardware effects the location of your pins, which you will need in the clock pin step.

	To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf.		To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf.

	~~The clock needs~~ to ~~be assigned~~ to a pin. If the ~~clock speed~~ is ~~changed~~, ~~you need~~ to ~~do something with PLLs~~. ~~(both unconfirmed, someone with more info?)~~		To make the code compile properly on an different device (not a DE2-115), you need to set the osc_clk pin to the clock pin of your device. ''This can be read from the device manual''! On an DE0-Nano this pin is PIN_R8. This pin location varies between devices and you ''must'' look it up in your device manual. To set the pin location, open the assignment editor add new osc_clk and set its location to the pin ''specified in your manual'', ie. for DE0-nano this is R8. For the DE2-115 this is PIN_Y2.


	== Programming the FPGA ==		== Programming the FPGA ==
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	=== Altera ===		=== Altera ===

	~~To mine on a device other then DE115, you need to edit mine.tcl (under scripts/mine) and set the following bits to the correct values.~~		The new mining and programming scripts find the connected devices now. Just edit the config.tcl to have your details.

	~~proc find_instances {} {~~
	~~global instances~~
	~~foreach instance [get_insystem_source_probe_instance_info -hardware_name "USB-Blaster \[1-4.6\]" -device_name "@1: EP3C25/EP4CE22 (0x020F30DD)"] {~~
	~~dict set instances [lindex $instance 3] [lindex $instance 0]~~
	}


	~~And~~

	~~start_insystem_source_probe -hardware_name "USB-Blaster \[1-4.6\]" -device_name "@1: EP3C25/EP4CE22 (0x020F30DD)"~~

	~~To point to the correct device.~~ The ~~correct data for this can be found with jtagconfig --enum. Do not forget to add 0x to the beginning of the hex code of the device that you get with jtagconfig.~~

	~~Then change the connection details marked with "EDIT THESE"~~

	~~Linux tclcurl is not included in the directory,~~ and ~~on some distros like Arch it does not exist in~~ the ~~repositories~~. ~~The original authors site is down, but you can get it from debian repositories. Then just unpack and copy to~~ the ~~same directory as mine~~.tcl~~. Remember~~ to ~~get bin32 version, since quartus is 32bit only~~.

	==See Also==		==See Also==

Fikaloii at 04:32, 26 July 2011

2011-07-26T04:32:49Z

← Older revision		Revision as of 04:32, 26 July 2011
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	$ sudo jtag		$ sudo jtag

	> cable UsbBlaster		> cable UsbBlaster

	> bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd		> bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd

	> detect		> detect

	> svf fpgaminer.svf		> svf fpgaminer.svf

Fikaloii at 04:11, 26 July 2011

2011-07-26T04:11:52Z

← Older revision		Revision as of 04:11, 26 July 2011
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	On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules.		On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules.

	#####altera usb blaster		#####altera usb blaster
	BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster"		BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster"

Fikaloii at 04:10, 26 July 2011

2011-07-26T04:10:30Z

← Older revision		Revision as of 04:10, 26 July 2011
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	== Programming the FPGA ==		== Programming the FPGA ==

	On linux you need to set udev rules for the UsbBlaster cable to work.		On linux you need to set udev rules for the UsbBlaster cable to work. Under arch these are under /etc/udev/rules.d/ add a file called 51-altera.rules.

	#altera usb blaster		#####altera usb blaster
	BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster"		BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster"

Fikaloii at 04:01, 26 July 2011

2011-07-26T04:01:59Z

← Older revision		Revision as of 04:01, 26 July 2011
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	A miner that makes use of a compatible FPGA Board. The miner works either in a [[Pooled Mining\|mining pool]] or solo.		A miner that makes use of a compatible FPGA Board. The miner works either in a [[Pooled Mining\|mining pool]] or solo.

	This is the first open source FPGA ~~Bitcion~~ miner. It was released on May 20, 2011<ref>[http://forum.bitcoin.org/index.php?topic=9047.0 Official Open Source FPGA Bitcoin Miner (Just Released!)]</ref>.		This is the first open source FPGA Bitcoin miner. It was released on May 20, 2011<ref>[http://forum.bitcoin.org/index.php?topic=9047.0 Official Open Source FPGA Bitcoin Miner (Just Released!)]</ref>.

			== Software needed ==

			Currently programming and running the FPGAminer code requires Quartus II for Altera devices and Xilinx ISE Webpack for Xilinx devices. Quartus is 32bit only. The free ISE Webpack does not work on devices larger then Spartan6 LX75.

	== Compiling ==		== Compiling ==
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	== Programming the FPGA ==		== Programming the FPGA ==

			On linux you need to set udev rules for the UsbBlaster cable to work.

			#altera usb blaster
			BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", MODE="0666", SYMLINK+="usbblaster"



	=== Altera ===		=== Altera ===
	Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory.		Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory.

			=== Using urjtag ===

			(unconfirmed to work, lights blink though)

			$ sudo jtag
			> cable UsbBlaster
			> bsdl path /usr/share/urjtag/bsdl/EP4CE22F17C6_pre.bsd
			> detect
			> svf fpgaminer.svf

	== Mining ==		== Mining ==
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	Then change the connection details marked with "EDIT THESE"		Then change the connection details marked with "EDIT THESE"

			Linux tclcurl is not included in the directory, and on some distros like Arch it does not exist in the repositories. The original authors site is down, but you can get it from debian repositories. Then just unpack and copy to the same directory as mine.tcl. Remember to get bin32 version, since quartus is 32bit only.

	==See Also==		==See Also==

Fikaloii: corrections

2011-07-26T03:41:08Z

corrections

← Older revision		Revision as of 03:41, 26 July 2011
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	== Compiling ==		== Compiling ==

	= Altera =		=== Altera ===
	To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf.		To get the provided code to compile on a smaller device, you need to set CONFIG_LOOP_LOG2 to a value between 0-5. Higher values shrink the size in so that 4 does approx. 12000 LUTs large program, while 0 is around 90000 LUTs. CONFIG_LOOP_LOG2 is set in the file fpgaminer.qsf. The fpgaminer_top.v file also has a similar setting, but it is an ifdef/it does not get set from there if the setting exists in the qsf.

Line 12:		Line 12:
	== Programming the FPGA ==		== Programming the FPGA ==

	= Altera =		=== Altera ===
	Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory.		Copy the .sof file from the quartus output directory under your project directory to the scripts/program directory and execute <path>/quartus_stp -t program.tcl, then select the device you want programmed and then the sof file you moved to the directory.

	== Mining ==		== Mining ==

	= Altera =		=== Altera ===

	To mine on a device other then DE115, you need to edit mine.tcl (under scripts/mine) and set the following bits to the correct values.		To mine on a device other then DE115, you need to edit mine.tcl (under scripts/mine) and set the following bits to the correct values.
Line 26:		Line 26:
	dict set instances [lindex $instance 3] [lindex $instance 0]		dict set instances [lindex $instance 3] [lindex $instance 0]
	}		}
	}

	And		And