ASIC - Revision history

Luke-jr: Remove scamcoin promotion

2019-04-24T00:26:22Z

Remove scamcoin promotion

← Older revision		Revision as of 00:26, 24 April 2019
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	An '''application-specific integrated circuit''' (abbreviated as '''ASIC''') is an [[wikipedia:integrated circuit\|integrated circuit]] (IC) customized for a particular use, rather than intended for general-purpose use. In [[Mining hardware comparison\|Bitcoin mining hardware]], ASICs were the next step of development after [[Why a GPU mines faster than a CPU\|CPUs, GPUs]] and [[FPGA\|FPGAs]]. Capable of easily outperforming the aforementioned platforms for Bitcoin [[mining]] in both speed and efficiency, all Bitcoin mining hardware that is practical in use will make use of one or more Bitcoin ([[Block hashing algorithm\|SHA256d]]) ASICs.		An '''application-specific integrated circuit''' (abbreviated as '''ASIC''') is an [[wikipedia:integrated circuit\|integrated circuit]] (IC) customized for a particular use, rather than intended for general-purpose use. In [[Mining hardware comparison\|Bitcoin mining hardware]], ASICs were the next step of development after [[Why a GPU mines faster than a CPU\|CPUs, GPUs]] and [[FPGA\|FPGAs]]. Capable of easily outperforming the aforementioned platforms for Bitcoin [[mining]] in both speed and efficiency, all Bitcoin mining hardware that is practical in use will make use of one or more Bitcoin ([[Block hashing algorithm\|SHA256d]]) ASICs.

	Note that Bitcoin ASIC chips generally can ''only be used for Bitcoin mining''. While there are rare exceptions - for example chips that mine both Bitcoin and ~~Litecoin~~ - this is often because the chip package effectively has two ASICs: one for Bitcoin and one for ~~Litecoin~~.		Note that Bitcoin ASIC chips generally can ''only be used for Bitcoin mining''. While there are rare exceptions - for example chips that mine both Bitcoin and scrypt - this is often because the chip package effectively has two ASICs: one for Bitcoin and one for scrypt.

	The ASIC chip of choice determines, in large part, the cost and efficiency of a given miner, as ASIC development and manufacture are very expensive processes, and the ASIC chips themselves are often the components that require the most power on a Bitcoin miner.		The ASIC chip of choice determines, in large part, the cost and efficiency of a given miner, as ASIC development and manufacture are very expensive processes, and the ASIC chips themselves are often the components that require the most power on a Bitcoin miner.

Sunnankar: /* References */ Add references

2015-05-29T00:43:51Z

References: Add references

← Older revision		Revision as of 00:43, 29 May 2015
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	== References ==		== References ==
	<references />		<references />

			* [https://www.bitcoinmining.com/ Bitcoin Mining]
			* [https://www.youtube.com/watch?v=GmOzih6I1zs Video: What is Bitcoin Mining]

	[[Category:Hardware]]		[[Category:Hardware]]
	{{wp\|Application-specific_integrated_circuit}}		{{wp\|Application-specific_integrated_circuit}}

TheRealSteve: < ASICs list moved to article 'List of Bitcoin mining ASICs'

2015-05-18T20:48:55Z

< ASICs list moved to article 'List of Bitcoin mining ASICs'

Show changes

TheRealSteve: /* KnCMiner Sweden AB */

2015-05-11T17:08:37Z

KnCMiner Sweden AB

← Older revision		Revision as of 17:08, 11 May 2015
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	\|style=compact		\|style=compact
	\|dev=[[KnCMiner]],,Logo-kncminer.png		\|dev=[[KnCMiner]],,Logo-kncminer.png
	\|codevs=Alchip Technologies, Ltd (世芯电子)~~, Ltd~~		\|codevs=Alchip Technologies, Ltd (世芯电子)
	\|chip=Solar,http://www.kncminer.com/blog/newsarchive#announcing-solar-a-step-change-in-processing-capability,February 3rd 2015,https://bitcointalk.org/index.php?topic=864378.0		\|chip=Solar,http://www.kncminer.com/blog/newsarchive#announcing-solar-a-step-change-in-processing-capability,February 3rd 2015,https://bitcointalk.org/index.php?topic=864378.0
	\|mining=:0.07J		\|mining=(800/1000*5000):0.07J@:800Hz
	\|die=TSMC,16,,		\|die=TSMC,16nm,,8.4mmx16.4mm
	\|sources=date/Alchip/foundry<ref>http://www.kncminer.com/blog/newsarchive#accel-investing-in-kncminer-16nm-tape-out-completed</ref>		\|sources=date/Alchip/foundry<ref>http://www.kncminer.com/blog/newsarchive#accel-investing-in-kncminer-16nm-tape-out-completed</ref>, die size,Hz/Gh(derived)<ref>http://ww3.sinaimg.cn/large/7c2c00e3jw1ervfedx421j20t412ttbd.jpg</ref>
	\|warning=needinfo,As this chip is claimed to exist by a reputable party (KnCMiner AB), the information in this template requires expansion.		\|warning=needinfo,As this chip is claimed to exist by a reputable party (KnCMiner AB), the information in this template requires expansion.
	}}		}}

TheRealSteve: /* LK Group */ +name for B-eleven

2015-04-30T23:19:18Z

LK Group: +name for B-eleven

← Older revision		Revision as of 23:19, 30 April 2015
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	\|style=oneliner		\|style=oneliner
	\|dev=[[LK Group\|LK Group Limited]],http://www.lketc.com/enindex.aspx,Logo-lkgroup.png		\|dev=[[LK Group\|LK Group Limited]],http://www.lketc.com/enindex.aspx,Logo-lkgroup.png
	\|chip=,,,https://bitcointalk.org/index.php?topic=1033676		\|chip=B-eleven,,,https://bitcointalk.org/index.php?topic=1033676
	\|die=,14,,		\|die=,14,,
	\|warning=future,Plans for this chip have been announced<ref>http://www.weibo.com/1064916230/Ce24u30D8?from=page_1005051064916230_profile&wvr=6&mod=weibotime</ref> but it has not yet been manufactured. Any specifications are highly subject to change.		\|warning=future,Plans for this chip have been announced<ref>http://www.weibo.com/1064916230/Ce24u30D8?from=page_1005051064916230_profile&wvr=6&mod=weibotime</ref> but it has not yet been manufactured. Any specifications are highly subject to change.

TheRealSteve: /* SFARDS */ +package size, +presumed die size, =marking fix

2015-04-30T09:48:38Z

SFARDS: +package size, +presumed die size, =marking fix

← Older revision		Revision as of 09:48, 30 April 2015
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	\|pics=Asic-sfards-sf3301-top.png:Top,Asic-sfards-sf3301-bottom.png:Bottom		\|pics=Asic-sfards-sf3301-top.png:Top,Asic-sfards-sf3301-bottom.png:Bottom
	\|mining=36Gh:(10.98/36)J@0.6V:225Hz,100Gh:(53.60/100)J@0.8V:625Hz,72Gh:(23.28/72)J@0.6V:450Hz,152Gh:(97.28/152)J@0.8V:950Hz		\|mining=36Gh:(10.98/36)J@0.6V:225Hz,100Gh:(53.60/100)J@0.8V:625Hz,72Gh:(23.28/72)J@0.6V:450Hz,152Gh:(97.28/152)J@0.8V:950Hz
	\|package=FCBGA529*,,SF3301-FC481 / ~~0502043~~[date]2M		\|package=FCBGA529*,19x19mm,SF3301-FC481 / Q502043[date]2M
	\|codes=1513		\|codes=1513
	\|die=,28nm,,		\|die=,28nm,,10.56x10.52mm
	\|notes=This chip can perform SHA256(d) and Scrypt calculations. The performance figures are strictly for the SHA256(d) portion.<br />Date is tape-out date.<br />See also: GridChip, GridSeed.		\|notes=This chip can perform SHA256(d) and Scrypt calculations. The performance figures are strictly for the SHA256(d) portion.<br />Die size is silicon area (10.56x10.52mm)<br />Date is tape-out date.<br />See also: GridChip, GridSeed.
	\|sources=node size<ref>http://www.sfards.com/detail?id=22</ref>,specs<ref>https://bitcointalk.org/index.php?topic=985400.msg11083827#msg11083827</ref>,performance<ref>https://github.com/sfards/ASIC-SF3301/blob/master/SF3301_Power_Report_v0.5.pdf</ref>		\|sources=node size<ref>http://www.sfards.com/detail?id=22</ref>,specs<ref>https://bitcointalk.org/index.php?topic=985400.msg11083827#msg11083827</ref>,performance<ref>https://github.com/sfards/ASIC-SF3301/blob/master/SF3301_Power_Report_v0.5.pdf</ref>
	}}		}}

TheRealSteve: /* SFARDS */ updated performance specs

2015-04-30T09:37:56Z

SFARDS: updated performance specs

← Older revision		Revision as of 09:37, 30 April 2015
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	\|datasheet=[https://github.com/sfards/ASIC-SF3301 datasheet github repository]		\|datasheet=[https://github.com/sfards/ASIC-SF3301 datasheet github repository]
	\|pics=Asic-sfards-sf3301-top.png:Top,Asic-sfards-sf3301-bottom.png:Bottom		\|pics=Asic-sfards-sf3301-top.png:Top,Asic-sfards-sf3301-bottom.png:Bottom
	\|mining=~~152Gh~~,:0.~~19J~~,@0.8V,		\|mining=36Gh:(10.98/36)J@0.6V:225Hz,100Gh:(53.60/100)J@0.8V:625Hz,72Gh:(23.28/72)J@0.6V:450Hz,152Gh:(97.28/152)J@0.8V:950Hz
	\|package=FCBGA529*,,SF3301-FC481 / 0502043[date]2M		\|package=FCBGA529*,,SF3301-FC481 / 0502043[date]2M
	\|codes=1513		\|codes=1513
	\|die=,28nm,,		\|die=,28nm,,
	\|notes=This chip can perform SHA256(d) and Scrypt calculations. The performance figures are strictly for the SHA256(d) portion.<br />Date is tape-out date.<br />See also: GridChip, GridSeed.		\|notes=This chip can perform SHA256(d) and Scrypt calculations. The performance figures are strictly for the SHA256(d) portion.<br />Date is tape-out date.<br />See also: GridChip, GridSeed.
	\|sources=node size<ref>http://www.sfards.com/detail?id=22</ref>,specs<ref>https://bitcointalk.org/index.php?topic=985400.msg11083827#msg11083827</ref>		\|sources=node size<ref>http://www.sfards.com/detail?id=22</ref>,specs<ref>https://bitcointalk.org/index.php?topic=985400.msg11083827#msg11083827</ref>,performance<ref>https://github.com/sfards/ASIC-SF3301/blob/master/SF3301_Power_Report_v0.5.pdf</ref>
	}}		}}

TheRealSteve: /* SFARDS */ +datasheet repo for SF3301

2015-04-30T09:24:17Z

SFARDS: +datasheet repo for SF3301

← Older revision		Revision as of 09:24, 30 April 2015
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	\|dev=SFARDS,,Logo-sfards.png		\|dev=SFARDS,,Logo-sfards.png
	\|chip=SF3301,,March 10 2015,https://bitcointalk.org/index.php?topic=985400		\|chip=SF3301,,March 10 2015,https://bitcointalk.org/index.php?topic=985400
			\|datasheet=[https://github.com/sfards/ASIC-SF3301 datasheet github repository]
	\|pics=Asic-sfards-sf3301-top.png:Top,Asic-sfards-sf3301-bottom.png:Bottom		\|pics=Asic-sfards-sf3301-top.png:Top,Asic-sfards-sf3301-bottom.png:Bottom
	\|mining=152Gh,:0.19J,@0.8V,		\|mining=152Gh,:0.19J,@0.8V,

TheRealSteve: /* Bitmain Technologies Ltd. */

2015-04-23T11:04:27Z

Bitmain Technologies Ltd.

← Older revision		Revision as of 11:04, 23 April 2015
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	\|die=,28nm,,		\|die=,28nm,,
	\|package=Sawn FCQFN56*,8x8mm,Antminer logo / BM1382 / [lot/'''date''']		\|package=Sawn FCQFN56*,8x8mm,Antminer logo / BM1382 / [lot/'''date''']
	\|codes=~~A100114w1~~		\|codes=A10014P1,A10014Z2
	\|notes=Bitmain considers this their 'Gen 2' product.<br />This chip uses a custom physical pin configuration that should be treated as a QFN with multiple exposed pads.		\|notes=Bitmain considers this their 'Gen 2' product.<br />This chip uses a custom physical pin configuration that should be treated as a QFN with multiple exposed pads.
	\|sources=date, performance<ref>https://www.bitmaintech.com/support.htm?pid=007201406210452505098o0UWHKV0661</ref>		\|sources=date, performance<ref>https://www.bitmaintech.com/support.htm?pid=007201406210452505098o0UWHKV0661</ref>,codes: 14Z2<ref>https://farm8.staticflickr.com/7592/17214290116_b1eb7387d2_o.jpg</ref>
	}}		}}
	{{asic		{{asic

TheRealSteve: +LK Group

2015-04-22T00:25:28Z

+LK Group

@@ Line 666: / Line 666: @@
 |sources=date/node size/specs/package<ref>http://landasic.com/doc/info/view.php?id=102&cata=110</ref>
 }}
 === SFARDS ===